1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more specifically to a method for forming a cylindrical stacked capacitor in a semiconductor integrated circuit memory.
2. Description of Related Art
As one of semiconductor integrated circuit memory cells having a high integration density, a so-called one-transistor type dynamic memory cell, composed of one transistor and one capacitor, is widely used, since it is constituted of a small number of circuit elements, and therefore, since a necessary memory cell area can be easily reduced. In the following, this type of memory cell will be called simply a "memory cell".
In this type of memory cell, the magnitude of an output voltage obtained from the memory cell is in proportion to the capacitance of the capacitor. Therefore, in order to ensure a stable operation, even if the size of the memory cell is reduced so as to elevate the integration density, it is necessary to maintain the capacitance of the capacitor at a sufficiently large value.
Referring to FIG. 1, there is shown one example of conventional memory cell envisaged to have a large capacitance of capacitor. In FIG. 1, not only the capacitor but also a MOS transistor connected to the capacitor are shown. The shown capacitor includes (1) a storage electrode constituted of a conductive member 8 contacted to an N-type source/drain region 5A and constituting a support or base member, and a cylindrical conductive member 9 connected to the base conductive member 8, (2) a cell plate 11, and (3) a dielectric film 10 insulating between the cell plate 11 and the storage electrode 8 and 9. A device isolation is made by a field isolation silicon oxide film 2 selectively formed on a P-type silicon substrate 1.
The MOS transistor includes a pair of N-type source/drain regions 5A and 5B formed in the P-type silicon substrate 1 separately from each other, and a gate electrode 4 formed on a gate oxide film 3 covering the surface of a region between the pair of N-type source/drain regions 5A and 5B. The gate electrode 4 also functions as a word line. In addition, a bit line (not shown) is connected to the N-type source/drain region 5B through a contact hole (not shown) formed through a first interlayer insulator film 6 and a second interlayer insulator film 7.
In this shown structure, the storage electrode of the capacitor is in a cylindrical form composed of the base conductive member 8 and the cylindrical conductive member 9. Therefore, not only an outer wall surface of the cylinder but also an inter wall surface of the cylinder can be utilized to constitute a capacitor. Accordingly, it is considered to be possible to give a sufficient capacitance value while effectively suppressing an increase of the memory cell area.
One process for forming the above mentioned cylindrical storage electrode is proposed by Wakamiya et al, "NOVEL STACKED CAPACITOR CELL FOR 64 Mb DRAM", 1989 Symposium on VLSI Technology Digest of Technical Papers, Pages 69-70, the disclosure of which is incorporated by reference in its entirety into this application. This process will be now described with reference to FIGS. 2A to 2C.
As shown in FIG. 2A, after the MOS transistor has been formed, a conductive member 8 contacted to the N-type source/drain region 5A is formed. Then, as shown in FIG. 2B, a silicon oxide film 15 having a substantial thickness is formed on the whole surface, and an opening is formed through the silicon oxide film 15 so as to expose a substantial portion of the conductive member 8. In addition, a conductive film 9A of a polysilicon is deposited on the silicon oxide film 15 and the conductive member 8 exposed in the opening. Furthermore, the conductive film 9A is etched back by a dry etching so as to form a conductive member 9 deposited on only an inner wall surface of the opening formed in the silicon oxide film 15, as shown in FIG. 2C. Then, the silicon oxide film is removed so that an upstanding cylindrical conductive member 9 remains. Thereafter, the dielectric film 10 and the cell plate 11 are formed as shown in FIG. 1.
In the above mentioned etch-back process, in order to prevent the conductive film 9A from being left on an upper surface of the silicon oxide film 15, it is necessary to over-etch the conductive film 9A as shown in FIG. 2C. In fact, however, the amount of this over-etching varies in the same chip and from one memory chip to another in the same wafer, by 10% or more. As a result, a variation occurs in the height of the cylindrical conductive member 9 which constitutes the storage electrode.
Here, since the height of the cylindrical conductive member 9 directly influences the capacitance value of the capacitor formed, a variation in the capacitance value of the capacitor formed in accordance with the above mentioned conventional process cannot be avoided. The variation in the capacitance value gives an adverse influence on a stable operation of the memory cells.
Accordingly, equalization of the amount of etch-back is very important to equalize the capacitance value of the capacitors, and therefore, to ensure the stable operation of the memory cells.